This application is related to Japanese application No. 2001-111818 filed on Apr. 10, 2001, whose priority is claimed under 35 USC xc2xa7 119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to an internal power voltage generating circuit of a semiconductor device.
2. Description of the Related Art
FIG. 4 is a functional block diagram showing a function of a conventional general semiconductor device.
Provided at the semiconductor device are a protection circuit 12 and an input-output circuit 13 in addition to a functional circuit 11 (such as a logic circuit, memory circuit, control circuit or the like) that takes charge of the original function. A signal S such as data or address is inputted to or outputted from the functional circuit 11 via the protection circuit 12 and the input-output circuit 13.
A power P is supplied from an external power supply to these protection circuit 12, input-output circuit 13 and functional circuit 11. Generally, a voltage set in advance is supplied to the functional circuit 11.
A semiconductor device is generally designed for allowing a margin so as to satisfy its specification with respect to a process variation upon manufacturing the device. However, it is difficult to design the device with the margin allowed, as the miniaturization has been advanced. Further, the more the miniaturization has been advanced, the greater the degree of the characteristic variation of each element becomes with respect to the process variation. Therefore, the design allowing this great characteristic variation becomes difficult. Consequently, a semiconductor chip or wafer that does not satisfy the specification has been manufactured, to thereby increase a possibility of reducing a yield.
A semiconductor device disclosed in Japanese Unexamined Patent Application No. Hei 6(1994)-326588 has been known as the one that prevents the reduction in the yield with respect to the process variation. This semiconductor device supplies, every semiconductor chip, an optimum operation voltage corresponding to the process variation, so that each semiconductor chip can be used under a nearly optimum condition. By this structure, the device aims to draw out the maximum performance of each semiconductor chip.
FIG. 5 is a view showing a circuit that generates internal power voltage of this semiconductor device. The circuit for generating the internal power voltage is consisted of a reference potential generating circuit 14 and a constant voltage circuit 15.
The reference potential generating circuit 14 includes a resistance R, a plurality of diodes D and a plurality of fuses F connected respectively in parallel to a portion of the diodes D. The reference potential generating circuit 14 divides the external power supply voltage Vcc via the resistance R and the diode D to thereby generate a reference voltage Vref.
The constant voltage circuit 15 is consisted of a current mirror circuit and a source follower circuit. The constant voltage circuit 15 outputs the internal power voltage Vint having the same potential as the reference potential Vref.
Disconnecting a portion of the fuses F generates a desired internal power voltage Vint in the circuit for generating the internal power voltage. When a silicon diode is used for the diode D, for example, electric current begins to flow at a forward bias of approximately 0.6 V per one diode, so that the reference potential Vref becomes a value obtained by multiplying approximately 0.6 V by a number of the diodes. By utilizing this, the fuse F is disconnected so as to change the number of the diodes D, to thereby change the value of the reference potential Vref.
However, the reference potential Vref is determined only by the values of the diode D and the resistance R in the above-mentioned voltage generating circuit, whereby it only takes a discrete number determined by the forward bias (voltage value of approximately 0.6 V) of the diode D. When a silicon diode is used as described above, for example, it only takes a value integral times as great as 0.6 V.
Further, a process for disconnecting the fuse F is required for selecting the optimum internal power voltage Vint, resulting in entailing a problem of increasing a manufacturing cost as well as lengthening a turnaround time (TAT) due to the increase in the number of a manufacturing process.
The present invention is accomplished in view of the above-mentioned circumstances, and aims to provide an internal power voltage generating circuit of a semiconductor device capable of supplying a suitable internal power voltage for drawing out a maximum performance of the semiconductor device without adding a process of disconnecting a fuse, even when a process variation occurs.
The present invention provides an internal power voltage generating circuit of a semiconductor device comprising a voltage dividing circuit composed of a single field effect transistor and a plurality of resistances incorporated into a semiconductor chip, wherein the voltage dividing circuit divides an externally supplied power voltage into two types of voltage by conducting or non-conducting the single field effect transistor, the divided voltages being supplied as an internal power voltage to a plurality of field effect transistors incorporated into the semiconductor chip.
According to the present invention, an externally supplied voltage is divided at a voltage dividing circuit into two types of voltage by conducting or non-conducting a single field effect transistor included in the voltage dividing circuit. The divided voltages are supplied as an internal power voltage to a plurality of field effect transistors incorporated into the semiconductor chip. This structure results in changing a value of the internal power voltage in accordance with a value of threshold voltage of the single field effect transistor, the value of threshold voltage having been varied due to a process variation during manufacture of the semiconductor chip.